ITC Mobile Conference Guide
Wednesday Technical Sessions, 2 p.m.
On this page:
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Session 16: Security Talks
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Session 17: 3D/TSV Reliability
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Session 18: Practical Applications of IEEE 1687
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Session 19: New Tests for Memory Test
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Elevator Talks
SESSION 16: Security Talks
Peilin Song, IBM T. J. Watson Research Center (Chair)
Room MKB1
16.1 On Securing the Embedded Test and Repair Infrastructure IP on Chip (invited)
Yervant Zorian, Synopsys
16.2 Trusted System Design with Untrusted Components (invited)
Swarup Bhunia, University of Florida
16.3 System-on-Chip Security Architecture and Validation: Current Practices and Emerging Trends (invited)
Sandip Ray, Intel
SESSION 17: 3D/TSV Reliability
Christos Papameletis, Cadence Design Systems (Chair)
Krishnendu Chakrabarty, Duke University (Firing Line)
Room MKB2
17.1 On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement
Li Jiang, Shanghai Jiao Tong University
17.2 Monitoring the Delay of Long Interconnects via Distributed TDC
Shi-Yu Huang, Nationa Tsing Hua University, Taiwan
17.3 Reliable 3D/2.5D IC Integration (invited)
Li Li, Cisco Systems
SESSION 18 : Practical Applications of IEEE 1687
Jeffrey Rearick, Advanced Micro Devices (Chair)
Jason Doege, Centaur Technology (Firing Line)
Room MKB3
18.1 A Case Study: Leverage IEEE 1687 based Method to Automate Modeling, Verification, and Test Access for Embedded Instruments in a Server Processor
Presenter: Tassanee Payakapan, Advanced Micro Devices
18.2 Access Time Minimization in IEEE 1687 Networks
Presenter: Rene Krenz-Baath, Lund University
18.3 An Approach to Automate Pattern Retargeting using IEEE 1687 (invited)
Presenter: Rajesh Khurana, Cadence Design System
SESSION 19: New Tests for Memory Test
Rubin Parekhji, Texas Instruments (Chair)
Sandeep Gupta, USC (Firing Line)
Room DGB South A & B
19.1 Testing Methods for Quaternary Content Addressable Memory Using Charge-Sharing Sensing Scheme
Presenter: Hao-Yu Yang, National Chiao Tung University
19.2 Stepped Parity: A Low-cost Multiple Bit Upset Detection Technique
Presenter: Mehdi Tahoori, Karlsruhe Institute of Technology
19.3 Optimizing Delay Tests at the Memory Boundary
Presenter: Kelly Ockunzzi, GLOBALFOUNDRIES
ELEVATOR TALKS
Yanjing Li, University of Chicago (Chair)
Room MKB4
Elevator talks offer participants very short time slots (with Q&A) to summarize their latest exciting ideas. The name of this session stems from the idea that it should be possible to deliver the summary within the time span of an elevator ride. ITC elevator talks include an impressive slate of academic and industrial presenters. These talks are very short, so don't be late or you might miss some highly exciting ones.
Enamul Amyeen, Intel Post silicon diagnosis revisited
Paolo Bernardi, Politecnico di Torino On-line Software-based Self-Test of Automotive Microcontrollers
Soumendu Bhattacharya, Cyberonics Test challenges with wearable technology
Sounil Biswas, nVidia Challenges with FPGA Testing - How does it compare to traditional ASIC and Micro-Processor Testing
Ian Harris, UC-Irvine Extracting Assertions Directly from Natural Language Specifications for Pre-silicon Verification
Ke Huang, San Diego State University Brain signal data mining: how test concepts can be applied for implementing efficient brain-computer interfaces
Shi-Yu Huang, National Tsing Hua University Cell-Based PLL Compiler for Test, Yield and Reliability Enhancement
Brion Keller, Cadence Advanced Fault Modeling for the sub-10 NM Era
Lorena Anghel, TIMA Laboratory Reliability measurements with in situ delay monitors in FDSOI technology
Peter Maxwell, ON Semiconductor Cell-aware diagnosis - examples of successful FA of internal cell defects
Huangxing Tang, Mentor New findings on test and diagnosis of open defects
Qiang Xu, Chinese University of HongKong Fault emulation platform to investigate the impact of soft errors and/or fault injection attacks on mission-critical ICs