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Poster Session Part 2, 12:00 noon

 

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Poster 2.1:   eFlash MCUs Multi-Temperature Coverage Maximization and Test Cost Optimization

Davide Appello,  ST Micro

 

Poster 2.2:   Open Defect Critical Area As a Function of Fan-Outs

Masayuki Arai,  Nihon University

 

Poster 2.3:   Leveraging Different Standards Together for Embedded Testing

Bill Atwell,  Silicon Aid

 

Poster 2.4:   Diagnosis in Low-Pin-Count TAM Architectures

Vivek Chickermane,  Cadence

 

Poster 2.5:   Device Characterization During Production Test Through Targeted Inline Data Collection

Cameron Cook,  Texas Instruments

 

Poster 2.6:   Dynamic Part Average Testing for Automotive IC Final Testing 

Wim Dobbelaere,  ON Semiconductor

 

Poster 2.7:   A Case Study of Low-Pin-Count Test Controller for Pin-Limited Low Power Designs 

Deepak Shetty, Cypress

 

Poster 2.8:   Withdrawn

 

 

Poster 2.9:   Final Test Solution of WLCSP Devices

Michael Frazier,  Xcerra

 

Poster 2.10:   Dynamic Versus Static Linear Encoding

Emil Gizdarski,  Synopsys

 

Poster 2.11:   Techniques to Improve Library Cell Defect Characterization

Ruifeng Guo,  Synopsys

 

Poster 2.12:   Combined Structural and Functional Test Coverage Concept Through PCOLASOQ-FAM

Buck Hoon Lau,  Intel

 

Poster 2.13:   On EDT Bandwidth Management with Dynamic Shift Cores 

Yu Huang,  Mentor Graphics

 

Poster 2.14:   Adaptive Soak Execution through Thermal Couplers for High-Parallelism Probe Card

Gyuyeol Kim,  Samsung

 

Poster 2.15:   ATPG: Maximizing Test Coverage Through Early DFT

Elizabeth Lillis,  Analog Devices

 

Poster 2.16:   Optimizing In-Circuit Test Cost Using Machine Learning and Test Sampling

Tony Lin,  Cisco Systems

 

Poster 2.17:   Enabling Plug-and-Play Architecture For Testing Chips Hierarchically

Kelly Ockunzzi,  GLOBALFOUNDRIES

 

Poster 2.18:   Innovative Methodology for Meeting Industrial Temperature Spec in Post-Silicon-Validation – Thermal Perspective

Ying Feng Pang,  Intel

 

Poster 2.19:   Flood-Filling Compression Hardware with Observation Flops

Raghuraman Rajanarayanan,  Achronix Semiconductor

 

Poster 2.20:   Concurrent Testing of Logic and Memory, and Detection of Memory Functional Paths in SOCs

Qihang Shi,  University of Connecticuit

 

Poster 2.21:   Low-Cost Ultra-Pure Sine Wave Generation with Self Calibration

Yuming Zhuang,  Iowa State University

  

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