ITC Mobile Conference Guide
Panel 1:
Is IEEE 1149.1 on Its Death Bed?
Room MKB 1 & 4
As device I/Os become faster and more customized, the capabilities of an IEEE 1149.1 interconnect test becomes marginalized. High-speed SerDes and photonics are putting 1149.1 on life support. Internal to the devices, built-in test instruments are requiring much more bandwidth as semiconductors explode in size and complexity. While standards are in the works for emerging 2.5-D and 3-D devices, the future is uncertain for 1149.1. An esteemed group of panelists will debate the fate of 1149.1 in light of these circumstances. We are expecting a lively and contentious discussion around this topic.
Ken Posse, Avago (Moderator & Organizer)
Ken holds a Bachelors in Aerospace Engineering, and a Masters in Computer Engineering and has over 35 years of experience in the electronics test industry. The last 18 years have been devoted to ASIC Design for Test with Hewlett Packard, Agilent Technologies, AMD, and now AVAGO Technologies. Ken is a Principle Engineer who currently is the DFT lead for AVAGO's 2.5-D effort. Position Statement: In recent years it has become clear that the IEEE 1149.1 universe has ceased to expand and is, in fact, collapsing. With new high-speed and highly specialized I/O logic together with standards (such as IEEE 1500 and IEEE 1687) that target logic circuits once handled solely by 1149.1, from a chip DFT perspective the utility of IEEE 1149.1 is rapidly decreasing. This, then, begs the question as to whether IEEE 1149.1 is in seriously declining health.
Following are the panelists and their biographies:
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Jason Doege (Centaur Technology): Jason ...
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William Eklow (Cisco Systems): William ...
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Teresa McLaurin (ARM ): Teresa
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Doug E. Olson (Keysight)
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Jeff Rearick (AMD): Jeff ...