2:00 Session | itc2015

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SESSION 1: Design and Data Optimization for Diagnosis

Chris Schuermyer, Synopsys (Chair)

Jeff Rearick, AMD (Firing Line)

Room MKB1

1.1 Design Reflection for Optimal Test-Chip Implementation

Presenter: Shawn Blanton, Carnegie Melon University

1.2 Efficient Observation-Point Insertion for Diagnosability Enhancement in Digital Circuits

Presenter: Sandeep Goel, TSMC

1.3 Information-Theoretic and Statistical Methods of Failure Log Selection for Improved Diagnosis

Presenter: Sarmad Tanwir, Virginia Tech

SESSION 2: Advanced Scan Testing

Shahrzad Mirkhani, University of Texas at Austin (Chair)

Naghmeh Karimi, Rutgers University (Firing Line)

Room MKB2

2.1 On Generating High Quality Tests Based on Cell Functions

Presenter: Xijiang Lin, Mentor Graphics Corp

2.2 Embedded Deterministic Test Points for Compact Cell-Aware Tests

Presenter: Jerzy Tyszer, Poznan University of Technology

2.3 Hierarchical DFT Methodology with Scan Pattern Retargeting (invited)

Presenter: Dan Trock, Annapurna Labs

SESSION 3: Analog/Mixed-Signal 1

Sounil Biswas, Altera (Chair)

Yiorgos Makris, University of Texas at Dallas (Firing Line)

Room MKB4

3.1 A New Method for Measuring Alias-Free Aperture Jitter in an ADC Output

Takahiro Yamaguchi, Advantest Laboratories

3.2 Evaluation of Low-Cost Mixed-Signal Test Techniques for Circuits with Long Simulation Times

Manuel J. Barragan, TIMA, CNRS/Université Grenoble-Alpes

3.3 Practical Analog Fault Simulation (invited)

Stephen Sunter, Mentor Graphics

IEEE TTTC E. J. McCluskey Doctoral Dissertation Competition: Final Round

Room MKB3

DDC1 Test and Debug Solutions for 3D- Stacked Integrated Circuits

Serge Deutsch, Duke University

DDC2 Cross-Layer Approaches for an Aging-aware Design of Nanoscale Microprocessors

Fabian Oboril, Karlsruhe Institute of Technology

DDC3 Yield and Reliability Enhancement for 3-D ICs

Li Jiang, Shanghai Jiao Tong University