12:00 Poster Sesson-1

Poster 1.1: RITdb-based Messaging - Real-Time Monitoring, Adaptive Test,…

Stacy Ajouri, Texas Instruments

Poster 1.2: Two-Pin Test with Overlapped Scan Using Manchester Encoding

Vivek Chickermane, Cadence

Poster 1.3: At-Speed Testing of Inter-Die Interconnects in 2.5D- and 3D-SICs

Vivek Chickermane, Cadence

Poster 1.4: Utilizing FPGAs as a Tester in 3D Stacked ICs

Jennifer Dworak, Southern Methodist University

Poster 1.5: Clock Control Placement for Hierarchical DFT and Pattern Retargeting

Rick Fisette, Mentor Graphics

Poster 1.6: ECMO: Error Clock-TSV Mending On-the-Fly

Tsung-Chu Huang, National Changhua University of Education, Taiwan

Poster 1.7: A New Approach to Automate ASIC Embedded IP Test in an IEEE 1687 Environment

Rajesh Khurana, Cadence

Poster 1.8: On-Chip Accurate and Effective Clock Frequency Checker

Inwoong Kim, Cisco Systems

Poster 1.9: Device Cost-effective Parallel LFSR for Test Pattern Generation Using GPU

Han Kyul Kim, Yonsei University

Poster 1.10: A Method to Debug Missed At-Speed Capture Clock Pulse of “On Chip Clock Controller” (OCC) in ATPG Mode

Vinay Kumar, ST Micro

Poster 1.11: Firmware-controlled Scan-Clock Gating for IOT Applications

Sanjay Kumar, Broadcom

Poster 1.12: Virtual Test: Simulating ATE Vectors in a SystemVerilog Testbench for Faster Time to

Market

John Mackintosh, Analog Devices

Poster 1.13: Adaptive Big-Data Scheme for Scan-Diagnostics-based Rapid Yield Learning

Jayasimha N Murthy, Broadcom

Poster 1.14: Test and Validation of Functional Safety Requirements by On-Board Fault Emulation

Thomas Nirmaier, Infineon

Poster 1.15: Hierarchical DFT with IJTAG on Hundred-Million Gate Design

Gavin Hun, Mediatek

Poster 1.16: IEEE 1687 iJTAG: Think beyond JTAG

Vishwanath Raja, Cisco Systems

Poster 1.17: Clock Jitter Cancelation in Coherent Data Converter Testing

Kars Schaapman, Applicos

Poster 1.18: Integration of IJTAG Test and Trim Islands in I²C Legacy Designs

Hans Martin Von Staudt, Dialog Semiconductor

Poster 1.19: XLBIST: Fully X-Tolerant Logic BIST in a Scan Compression Architecture

Peter Wohl, Synopsys

Poster 1.20: OFDM Multitone Signal Generation Technique for Analog Circuit Test Characterization

Tian Xia, University of Vermont

Poster 1.21: Implementing the CAST Test Event Messaging Standard
Keith Thomas, TEMS Working Group Chair, Teradyne