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Wenesday Technical Sessions, 8:30 a.m.

 

SESSION 6:   Room 602-4

More Test Compression: Cadence, Mentor, Synopsys

Xiaowei Li, Chinese Academy of Sciences (Chair)

 

6.1  Efficient Testing of Hierarchical Core-based SOCs

Presenter: Brion Keller,  Cadence Design Systems

Firing Line:  Rohit Kapur, Synopsys 

 

6.2  Isometric Test Compression with  Low Toggling Activity

Presenter: Jerzy Tyszer, Poznan University of Technology

Firing Line:  Samy Makar

 

6.3  Achieving Extreme Scan  Compression for SoC Designs

Presenter:  Peter Wohl, Synopsys

Firing Line:  Manish  Sharma, Mentor Graphics 

         

RATE SESSION 6

 

 

SESSION 7:   Room 608-9

Tackling Timing and Power During Test

Masanori Hashimoto, Osaka University (Chair)

 

7.1  Mitigating Voltage Droop During Scan with Variable Shift Frequency

Presenter: John Schulze, AMD

Firing Line: Pankaj Pant, Intel  

 

7.2  At-speed Capture Power Reduction  Using Layout-aware Granular Clock  Gate Enable Controls

Presenter: Srivaths Ravi, Texas Instruments

Firing Line:  Xiaoqing Wen, Kyushu Institute of Technology  

 

7.3  Fast BIST of I/O Pin AC Specifications  and Inter-Chip Delays

Presenter: Stephen Sunter, Mentor Graphics

Firing Line:  Paul Berndt, Cypress Semiconductor 

 

RATE SESSION 7

 

SESSION 8:   Room  615

Learn From The Experts: High Volume Manufacturing

Phil Nigh, IBM  (Chair)

 

8.1  Latent Defect Detection in Microcontroller-embedded Flash Test Using Device Stress and Wordline Outlier Screening

Presenter: Andreas Kux, Infineon Technologies

Firing Line:  Adit Singh, Auburn University

 

8.2  Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills

Presenter: Masahiro Ishida, Advantest

Firing Line: Bruce Parnas, Xcerra

 

8.3  (Invited) Challenges of Testing 100M Chips

Presenter: Sajjad  Pagarkar, Qualcomm

Firing Line: Jayashree Saxena, Anora

 

RATE SESSION 8

 

SESSION 9:  Room  618

RF Test: Digital ATE, Radios, Radars

Saghir Shaikh, Broadcom (Chair)

 

9.1  Low-Cost Phase Noise Testing of Complex RF ICs Using Standard Digital ATE

Presenter: Florence Azais  LIRMM

Firing Line: Mustapha Slamani, IBM

 

9.2  (Invited) Market Opportunities and Testing Challenges for Millimeter Wave Radios and Radars

Presenter: Brian  Floyd, North Carolina State University

Firing Line: Keith Schaub, Advantest

 

9.3   A Novel RF Self-Test for a Combo SoC on Digital ATE with Multisite  Applications

Presenter: Chun-Hsien Peng, MediaTek

Firing Line: Yiorgos Makris

 

 

RATE SESSION 9

 

 

IEEE TTTC Edward J. McCluskey Doctoral  Dissertation Competition: Final Round:  Room  606

Michele Portolan, INP Grenoble (Chair)

 

DDC 1 Error Prediction and Detection Methodologies for Reliable Circuit Operation under NBTI

Julio Vazquez-Hernandez, INAOE

 

DDC 2  DFST: Design for Secure Testability

 Samah Saeed, NYU Polytechnic

 

DDC 3  Analysis and Test of the Effects of Single-event Upsets Affecting the Configuration Memory of SRAM-based FPGAs

Luca Cassano, University of Pisa

 

RATE IEEE TTTC Edward J. McCluskey Doctoral  Dissertation Competition

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