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Tuesday Technical Sessions, 4 p.m.

 

SESSION 5:  Room 608-9

Discussion Session: Has Adaptive Test Lived Up To Its Expectations?

Dan Glotter, Optimal+ (Moderator); Jeff Roehr, Texas Instruments (Organizer)

 

5.1  (Invited) Concerns over Predictability  of Supply and Quality

Carl Bowen, AMD

 

5.2  (Invited) The Desire-Friction Ratio of Adaptive Test

Stacy Ajouri, Texas Instruments

 

5.3  (Invited) Collaboration and Teamwork Obstacles

Wesley Smith, Galaxy Semiconductor

 

5.4  (Invited) ATE and Test Equipment Vendors; Hardware Not Software

Mark Roos, Roos Instruments

 

RATE SESSION 5

 

 

 

PANEL 2:  Room 6E

Open Problems in Design, Verification and Test: Why Is It (Not) Business as Usual?

Tim Cheng, UC, Santa Barbara (Moderator);  Rubin Parekhji, Texas Instruments (Organizer)

 

Panelists with wide-ranging technical and business expertise will discuss open problems in design, verification and test. Solutions to these open problems are critical for future electronic systems that will incorporate massive integration of diverse functionality with unprecedented constraints on cost, power/performance, reliability and time-to-market. They will also debate whether existing design-EDA partnerships are adequate or a new ecosystem is required. 

 

Panelists  

Sanjive Agarwala, Texas Instruments

Paul  Cunningham, Cadence Design Systems  

Stephen  Pateras, Mentor Graphics

Ruchir Puri, IBM

Ramesh  Senthinathan, Broadcom

Srikanth Venkataraman, Intel

 

RATE PANEL 2

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