ITC Conference Guide
Wenesday Poster Session, 12:00 to 2:00
Poster 1: Two-Step Dynamic Encoding for Linear Decompressors
E. Gizdarski, Synopsys
Poster 2: Handling Xs in Test Simulation—A Case Study
K-H Chang*, Y-T Liu, C. Browy, Avery Design Systems
Poster 3: Multi-bit Delta-Sigma TDC BOST for Timing Test
H. Kobayashi*, T. Chujo, D. Hirabayashi, Gunma University; M. Tsuji, STARC; K. Sato, Kikari Science
Poster 4: Detection and Diagnostics of Anomalous Thermal Behavior in 28-nm High-Power SoC Devices
S. Dasnurkar*, N. Joshi, A. Devatha, K. Dusety, P. Bhadri, Qualcomm
Poster 5: System-level Test and Fault Isolation
J. Block*, T. Anayama, DCG Systems
Poster 6: Leveraging Design Pipelines in DFT
R. Rajanaray, SmartPlay Technologies, India
Poster 7: An Adaptive TMR Flip-Flop Architecture for Fault-Tolerance-Power Optimization
L. Cassano*, Politecnico di Milano; G. Di Natale, A. Bosio, LIRMM
Poster 8: Considerations for Assimilating Competing Standards
B. Atwell*, A. Bair, C. Barnhart, B. Bruce, J. Johnson, SiliconAid Solutions
Poster 9: Minimization of Yield Loss in Wafer Test by Separated I/O Channels in Probe Card with ASIC Analog Switches
S. Joo*, J. Kim, S. Yoo, J. Joo, Samsung Electronics
Poster 10: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices
Q. Khasawneh*, Texas Instruments; P. Gui, J. Dworak, SMU; Q. Zhao, Oncor
Poster 11: At-Speed Testing of Inter-Clock Domain Paths
S. Bahl*, S. Khullar, S. Rungta, STMicroelectronics, India
Poster 12: A Fault Injection Methodology for Single-Event Upsets Emulation of Xilinx SRAM-based FPGAs
D. Rolfo*, S. Di Carlo, P. Prinetto, P. Trotta, Politecnico di Torino
Poster 13: Core Self-Test Execution Management
P. Bernardi*, R. Cantoro, E. Sanchez, Politecnico di Torino; O. Ballan, S. De Luca, R. Meregalli, A. Sansonetti, STMicroelectronics
Poster 14: Improving ATPG Effectiveness Using Random Resistive Fault Analysis at RTL
S. Shaikh*, Broadcom
Poster 15: Detection and Screening of Small Delay Defects Impacting System Functionality in 28-nm/20-nm SoC
S.Dasnurkar*, A. Devatha, P. Bhadri, Qualcomm
Poster 16: Real-Time Supply Voltage Sensor for Trace-based Fault Localization
M. Hashimoto*, M. Ueno, T. Onoye, Osaka University
Poster 17: Group-Delay Testing for Envelope Tracking in a Radio Frequency Integrated Circuit
R. Rafique*, Ericsson Modem
Poster 18: Shadow Bin: A Test Executor on Steroids
V. Shirgur*, C. Mamuad, J. Sarmiento, G. Ponnuvel, NVIDIA
Poster 19: Rnv8T NVSRAM Test Time Reduction by Combining RRAM Forming and RRAM Defect Detection Prior to Functional Tests
B-C. Bai*, C-M Li, National Taiwan University; C-A Chen, Y-W Chen, M-H Wu, P-Y Chen, K-L Luo, C-L Hsu, L-C Cheng, C-M Li, ITRI
Poster 20: Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise
T. Zhang*, Y. Gao, D. M. H. Walker, Texas A&M University
Poster 21: A Production ATE Solution for Microwave and Millimeter Automotive Radar
D. Morris, Roos Instrument
Poster 22: Physical Design for Debug – A Low-Cost Method to Extend DFT
J. Giacobbe*, Intel
Poster 23: A Novel Scan-based Diagnostics Approach to Enable Rapid Yield Learning for Production Ramp
D. Wee*, J. Murthy, A. Aggarwal, M. Rathinasabapathy, N.C. Seow, S. Shaikh, G. Eves, Broadcom
Poster 24: Copula-based Techniques to Identify Miscorrelating Outlier Between Efficient Test and Use
Y-S. Wang*, W. R. Daasch, Portland State University
Poster 25: Emerging Test Standards
IEEE Standards Working Group Representatives
Poster 26: Enhanced OCC and Ideal Logic BIST
R. Rajanaray*, Consultant
Poster 27: Multi-Tier Power-aware Verification of SoC ICs
D. Akselrod*, S. Golubkov, P. Liu, Advanced Micro Devices
Poster 28: Intro to RITdb – Comprehensive Standards to Support Monitoring, Analysis and Adaptive Test
S. Ajouri*, Texas Instruments
Poster 29: Mixed-Signal Tester-on-Chip (ToC)
H. Ehrenberg*, T. Wenzel, J. Heiber, GOEPL Electronics
Poster 30: System-level Test of Complex SoC’s Using Protocol-aware ATE
S. Molavi*, Broadcom
Poster 31: IEEE 1687 (iJTAG) – Enabling In-System Test Automation
Y. Lee*, W. Wang, H. M. Li, Cisco Systems
Poster 32: Rapidly Sourcing Yield Excursions with Scan Analysis
E. McArthur*, Cypress Semiconductor; B. Keller, Mentor Graphics
Poster 33: Challenges and Chances in Network Reliability
Z. Zhang*, X. Gu, Z. Wang, X. Fan, G. Chen, T. Xu, X Liu, Huawei Technologies
Poster 34: System State Retention Verification Using ATPG for Debug
P. Venkitaraman*, J. Abraham, National AMD India
Poster 35: An Integrated Enterprise-wide Yield Monitoring and Root Cause Analysis System
D. Wee*, J-Y. Siow, J. Chan, M. Mattingly, G. Eves, Broadcom
Poster 36: Reducing the Effort for Board-level Functional Diagnosis Through Incremental Test Execution
L. Cassano*, C. Bolchini, Politecnico di Milano
Poster 37: An Extensible Low-Density Parity-Check Decoder for Solid-State-Drive
T. Kang*, H. Yi, Hanbat National Univ.
Poster 38: Fault Diagnosis Techniques for Defect Inside Library Cells
R. Guo*, C. Schuermyer, E. Gizdarski, Y. Kanzawa, Synopsis
Poster 39: Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits
S. Reddy*, University of Iowa; X. Lin, J. Rajski, Mentor Graphics
Poster 40: WLCSP Massive Parallel Test Solution
A. Monga*, H. Takuya, Advantest
Poster 41: Advanced Parametric Probe Challenges
S. Kuhnert*, R. Lakshmanan, Cascade Microtech
Poster 42: The Evolution of Waveform Generation, Measurement and Analysis, and Its Impact on Test
S. Tilden, Xcerra
Poster 43: Challenges in Testing MEMS Inertial Devices
R. Chrusciel, FocusTest