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Thursday Technical Sessions, 9:00 a.m.

 

SESSION 19:  Room 608-9

Statistical Approaches to AMS Design and Test

Ray Clancy, Broadcom (Chair)

 

19.1  Bayesian Model Fusion: Enabling Test Cost Reduction of Analog/RF Circuits via Wafer-level Spatial Variation Modeling

Presenter:  Shanghang Zhang, Carnegie  Mellon University

Firing Line: Yiorgos Makris, University of Texas at Dallas

 

19.2  IC Laser Trimming Speed-Up Through Wafer-level Spatial Correlation Modeling

Presenter:  Constantinos Xanthopoulos,Texas  Instruments

Firing Line: Li-C. Wang, UC, Santa Barbara

 

19.3  (Invited) Design and Test of Analog  Circuits Toward Sub-PPM Level

Presenter:  Georges Gielen, ON Semiconductor

Firing Line:  Abhijit Chatterjee, Georgia Tech

 

 

RATE SESSION 19

 

 

 

SESSION 20:  Room  615

Test and Yield Go 3-DL. Winemberg, Freescale Semiconductor

 

20.1  Redundancy Architectures for Channel-based 3D DRAM Yield Improvement

Presenter:  Bing-Yang Lin, National Tsing Hua University

Firing Line:  Yanjing Li, Intel 

 

20.2  Vesuvius-3D: A 3D-DFT Demonstrator

Presenter:  Erik Jan  Marinissen, IMEC

Firing Line:   Erik Larsson, Lund University

 

20.3  A Distributed, Reconfigurable and Reusable BIST Infrastructure for 3D-Stacked ICs

Presenter:  Mukesh Agrawal,  Duke University

Firing Line:  Erik Larsson, Lund University

 

 

 

RATE SESSION 20

 

 

SESSION 21:  Room 606

Boards and Test: Not Your Dad's Board Test

Zoe Conroy, Cisco Systems (Chair)

 

21.1  (Invited) Interposer Test: Testing PCBs That Have Shrunk 100X 

Presenter:  TM Mak, GLOBALFOUNDRIES

Firing Line:  William Eklow, Cisco Systems

 

21.2  Knowledge Discovery and Knowledge Transfer in Board-level Functional Fault Diagnosis

Presenter:  Fangming Ye, Duke University

Firing Line:  Li-C. Wang, UC, Santa Barbara

 

21.3  Board Manufacturing Test Correlation to IC Manufacturing Test

Presenter:  C. Glenn Shirley,Portland State

Firing Line:  Ralf Arnold, Infineon Technologies

 

 

 

RATE SESSION 21

 

 

 

SESSION 22: Room 602-4

Validation: Pre-Silicon, Emulation, Post-SiliconT. Chakraborty, Qualcomm (Chair)

Tapan Chakraborty, Qualcomm (Chair)

 

22.1  On-Chip Constrained Random Stimuli Generation for Post-Silicon Validation Using Compact Masks

Presenter: Xiaobing Shi, McMaster University;

Firing Line:  Matteo Sonza Reorda, Politecnico di Torino

 

22.2  (Invited) Emulation and Its Connection to Test

Presenter:  Kenneth Larsen, Mentor Graphics

Firing Line: Nicola Nicolici, McMaster University

 

22.3  Clustering-based Failure Triage for RTL Regression Debugging

Presenter:  Zissis Poulos, University of Toronto

Firing Line: Jacob Abraham, UT-Austin

 

 

RATE SESSION 22

 

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