ITC Conference Guide
Thursday Technical Sessions, 3:00 p.m.
SESSION 27: Room 608-9
Stay "Tuned" for Analog Testing
27.1 Testing Silicon TV Tuners on ATE Without TV Signal Generator
Presenter: Yongquan Fan, Silicon Labs
Firing Line: Mustapha Slamani, IBM
27.2 A Self-Tuning Structure for Buck Converters Based on Alternative Test
Presenter: Abhijit Chatterjee, Georgia Institute of Technology
Firing Line: John Carulli, GLOBALFOUNDRIES
27.3 Fast Co-test of Linearity and Spectral Performance with Noncoherent Sampled and Amplitude-Clipped Data
Presenter: DeGang Chen, Iowa State University
Firing Line: Haruo Kobayashi, Gunma University
SESSION 28: Room 615
Attacks and Countermeasures for Secure ChipsK. Huang, San Diego State University (Chair)
28.1 Board Security Enhancement Using New Locking SIB-based Architectures
Presenter: JenniferDworak, Southern Methodist University
Firing Line: Michail Maniatakos, NYU Abu Dhabi
28.2 Counterfeit IC Detection Using Light Emission
Presenter: Peilin Song, IBM
Firing Line: Michail Maniatakos, NYU Abu Dhabi
28.3 Test-Mode-only Scan Attack and Countermeasure for Contemporary Scan Architectures
Presenter: Samah Saeed, NYU Polytechnic School Engineering; Firing Line: M. Maniatakos, NYU Abu Dhabi,J. Dworak, Southern Methodist University
Firing Line: Jeniffer Dworak, Southern Methodist University
SESSION 29: Room 606
Logic test compression + Logic BIST
Michael Vachon, Cadence Design Systems (Chair)
29.1 Improving Test Compression with Scan Feedforward Techniques
Presenter: Sreenivaas Muthyala, University of Texas at Austin
Firing Line: Peter Wohl, Synopsys
29.2 A Diagnosis-friendly LBIST Architecture with Property Checking
Presenter: Sarvesh Prabhu, Virginia Tech
Firing Line: Manish Sharma, Mentor Graphics
29.3 FAST-BIST: Faster-than-At-Speed BIST Targeting Hidden Delay Defects
Presenter: Sybille Hellebrand, University of Paderborn
Firing Line: Krishna Chakravadhanula, Cadence Design Systems
SESSION 30: Room 602-4
What's Wrong with My Chip?
Eric Rentschler, Mentor Graphics (Chair)
30.1 An Efficient Diagnosis-aware Pattern Generation Procedure for Transition Faults
Presenter: Cheng-Hung Wu, National Cheng Kung University
Firing Line: Srikanth Venkataraman, Intel
30.2 Divide and Conquer Diagnosis for Multiple Defects
Presenter: Shih-Min Chao, National Taiwan University
Firing Line: W-T. Cheng, Mentor Graphics
30.3 Massive Signal Tracing Using On-Chip DRAM for In-System Silicon Debug
Presenter: Sergej Deutsch, Duke University
Firing Line: Yanjing Li, Intel