2:00 Session | 2016itc

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SESSION 10: Test Vehicle Design

S. Venkataraman, Intel (Chair)

R, Desineni, GLOBALFOUNDRIES (Discussant)

Room 201A

10.1 Logic Characterization Vehicle Design Reflection via Layout Rewiring
Presenter: P. Fynan, Carnegie Mellon University

10.2 Test Chip Design for Optimal Cell-aware Diagnosability
Presenter: S. Mittal, Carnegie Mellon University

10.3* Advanced Node Product and Technology Enablement Vehicles
Presenter: M. Bourland, Qualcomm

SESSION 11: ATE I

R. Arnold, Infineon (Chair)

P. Berndt, Cypress Semiconductor (Discussant)
Room 201BC

11.1 Mixed-Signal ATE Technology and Its Impact on Today's Electronic System Platforms
Presenter: G. Roberts, McGill University

11.2 Known-Good-Die Test Methods for Large, Thin, High-Power Digital Devices
Presenter: D. Armstrong, Advantest

11.3 Test-Time-efficient Group Delay Filter Characterization Technique Using a Discrete Chirped Excitation Signal
Presenter: P. Sarson, ams

SESSION 12 : Security

J. Dworak, Southern Methodist University (Chair)

P. Song, IBM (Discussant)

Room 202CD

12.1 Securing Digital Microfluidic Biochips by Randomizing Checkpoints
Presenter: J. Tang, New York University

12.2 Machine Learning-based Defense Against Process-aware Attacks on Industrial Control Systems
Presenter: A. Keliris, New York University

12.3 Recycled FPGA Detection Using Exclusive LUT Path Delay Characterization
Presenter: M. Alam, University of Florida

SESSION 13: Methodology

V. Chickerman, Cadence (Chair)

S. Sinha, Intel (Discussant)

Room 202A

13.1* Four Challenging Insights About Fault Coverage,

Presenter: J. Rearick, AMD

13.2* Advanced Test Methodology for Complex SoCs
Presenter: M. Yilmaz, NVIDIA

13.3* The DFT Challenges and Solutions for the ARM Mali-Mimir GPU
Presenter: P. Kulkarni, ARM

SPECIAL SESSION 7: Design, Test and Reliability of STT-MRAM

M. Tahoori, Karlsruhe Institute of Technology (Chair and Discussant)

Room 202B

S7.1* STTRAM Overview—Circuit and Architecture Perspective
Presenter: H.Naeimi, Intel

S7.2* BIST Design for Characterization and Testing of Embedded STT-MRAM
Presenter: S. Adham, TSMC

S7.3* Tailoring Design and Test Methodologies to Validate STT-MRAM as High-Performance Nonvolatile RAM
Presenter: S. Kang, Qualcomm

* Invited Talk