ITC Mobile Conference Guide
Tuesday Technical Sessions, 4:30 p.m - 6:00 p.m.
On this page:
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Special Session 2: 3D-IC Test Standard IEEE P1838
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Special Session 3: Test for Security and Trust
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Embedded Tutorial 1: Diagnosis to Failure Isolation: The Journey to Root Cause
SPECIAL SESSION 2: 3D-IC Test Standard IEEE P1838
S. Adham, TSMC (Chair)
A. Cron, Synopsys (Discussant)
Room 202A
S2.1* P1838 Overview
Presenter: E. J. Marinissen, IMEC
S2.2* Serial Control Mechanism
Presenter: A. Crouch
S2.3* Die Wrapper Register
Presenter: T. McLaurin, ARM
S2.4* Flexible Parallel Port
Presenter: A. Cron, Synopsys
S2.5* Description Languages
Presenter: S. Behatia, Google
SPECIAL SESSION 3: Test for Security and Trust
M. Tehranipoor, University of Florida (Chair)
Room 201A
S3.1* The Enemies of IC Security and Trust and How to Test Them
Presenter: B. Swarup, University of Florida
S3.2* Is Automated Testing the Panacea Cryptography Needs to Deliver Promised Security Assurances?
Presenter: A. Vassilev, NIST
S3.3* Hardware Security Assurance: Challenges and Opportunities
Presenter: A. Khatibzadeh, Intel
EMBEDDED TUTORIAL 1: Diagnosis to Failure Isolation: The Journey to Root Cause
R. Guo, Synopsys (Chair)
Room 202B
ET1.1* The Journey to Root Cause—Part I
Presenter: E. Amyeen, Intel
ET1.2* The Journey to Root Cause—Part II
Presenter: A. Maldonado, Intel
* Invited Talk
Panel 2: Phased Array 5G: Is Test Connected or Disconnected?
Room 201BC
The need for 1000x increase in mobile data rate led to a push for an evolution of wireless networks and a revolution in architecture to meet future demands. The current architecture needs some major changes to keep up with future data needs. Test methods and processes need to evolve to match the new 5G requirements in order to provide a high confidence to operators that the technology and services are implemented according to specification. This panel will highlight the 5G test challenges and explore possible future solutions to enable mass market production.
M. Roos, Roos Instruments (Moderator)
M. Slamani (Organizer)
Panelists:
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P. Cain, Keysight
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B. Floyd, North Carolina State University
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R. McAleenan, Advantest
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A. Roessler, Rohde & Schwarz
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M. Slamani, GLOBALFOUNDARIES
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C. White, National Instruments
Panel 3: Test Cost Reduction—Is There More to Cut?
Room 202CD
LSI testing is not just technology, but also it is a part of company management strategies. For example, some companies may use low cost ATE while others may use high-end mixed-signal ATEs as well as its associated services and know how. It also depends on applications of the DUT; for automotive application ICs, reliability and safety are very important and sufficient testing is required. The figure of merit for LSI testing may be test quality / test cost. In this panel, several possible LSI testing methods in terms of test cost reduction will be discussed.
H. Kobayashi (Moderator and Organizer)
Panelists:
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R. Bartlett, Advantest
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W. Dobbelaere, ON Semiconductor
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R. Knoth, Cadence
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R. van Rijsinge, NXP Semiconductors
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P. Sarson, ams